The present invention relates generally to semiconductor device processing and, more particularly to interconnect structures having air gaps between adjacent conductive lines.
The evolution of integrated circuits toward higher complexity and decreased size has lead to closer spacing between the conducting wires (lines). Resulting capacitance increase produces time delays and creates cross-talk between the wiring elements. Current semiconductor fabrication techniques typically comprise many conductive wiring levels to complete the final working integrated circuits.
Semiconductor devices are typically joined together to form useful circuits using what is called “interconnect structures.” These interconnect structures are typically made of conductors such as copper (Cu) or aluminum (Al) and dielectric materials such as silicon dioxide (SiO2). The speed of these interconnects can be roughly assumed to be inversely proportional to the product of the line resistance (R), and the capacitance (C) between lines. To reduce the delay and increase the speed, it is desirable to reduce the capacitance (C). This can be done by reducing the dielectric constant (k), of the dielectric material due to the relationship C=kεoA/d, where εo is a universal constant, A is the coupling area, and d is the distance between two conductors. Decreasing the dielectric constant (k) leads to a direct decrease in capacitance (C). Conventional silicon dioxide has a dielectric constant (k) of approximately 4.1. A variety of “low-k” materials are known, such as SiLK™, an organic polymer with k=2.65 sold by Dow Chemical, and Black Diamond™, a organosilicon glass with k of 2.7 to 3.0, sold by Applied Materials.
RC (resistance-capacitance resonant) losses in the wiring levels of integrated circuits (ICs) make significant contributions limiting the final performance of the final semiconductor product. Therefore, the overall performance can be improved by reducing these RC losses. Using low-k materials such as SICOH, SILK are currently use as the dielectric between the metal line but air voids introduce ways to decrease these capacitance losses even further. Many techniques have been proposed to produce these structures—for example U.S. Pat. Nos. 6,316,347; 6,380,106; 6,498,070; and 5,923,074 often using the decomposition of polymeric layer to create these gaps.
Commonly-owned U.S. Pat. No. 6,472,740 discloses self-supporting air bridge interconnect structure for integrated circuits. A method for forming a multilevel interconnect structure for an integrated circuit is disclosed. In an exemplary embodiment of the invention, the method includes forming a starting structure upon a substrate, the starting structure having a number of metallic conducting lines contained therein. A disk is bonded to the top of said starting structure, the disk including a plurality of mesh openings contained therein. The mesh openings are then filled with an insulative material, thereby forming a cap upon the starting structure, wherein the cap may structurally support additional interconnect layers subsequently formed there atop.
U.S. Pat. No. 6,261,942 discloses dual metal-oxide layer as air bridge. A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.
U.S. Pat. No. 6,316,347 discloses air gap semiconductor structure and method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.
U.S. Pat. No. 6,380,106 discloses method for fabricating an air gap metallization scheme that reduces inter-metal capacitances of interconnect structures. A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material is described. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. The filler material is etched back to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, the filler material is vaporized, changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the permeable dielectric layer.
U.S. Pat. No. 6,498,070 discloses air gap semiconductor structure and method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.
U.S. Pat. No. 5,923,074 discloses low capacitance interconnect structure for integrated circuits using decomposed polymers. A low capacitance interconnect structure and process is provided for integrating low-k decomposed polymers into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines, for reduced capacitance over prior art structures. Embodiments use polymers which typically decompose into gases with lower dielectric coefficients than the original polymer to provide a lower dielectric constant material between conductive interconnects on an integrated circuit. The materials are decomposed after being sealed in with a cap layer to prevent contamination of the gas filled void left after decomposition. The technique also combines the advantages of SiO2 with low dielectric decomposed polymers by placing the low decomposed material only between tightly spaced lines. The low-k polymer material can be applied by spin-on techniques or by vapor deposition.